Vulcan's Trials

KiCad 8 / 9 / 10 Rust + Vulkan + CUDA GPL-3.0-only

Vulcan's Trials (vulcans-trials) is a unified, hardware-accelerated PCB Auto-Placer and 3D Negotiated-Congestion Auto-Router for KiCad. Built in Rust with Vulkan WGSL compute shaders, native NVIDIA CUDA PTX kernels, and multithreaded CPU Parallel Tempering, it brings flagship commercial EDA place-and-route capabilities to open-source hardware design.

View on GitHub → Releases & Packages Installation Guide

Why Vulcan’s Trials?

Traditional open-source PCB autorouters rely on single-threaded or purely geometric maze routing that ignores schematic intent, struggles with fine-pitch modern packages (QFN, BGA, USB-C), and lacks high-speed signal integrity constraints. Meanwhile, component placement—which dictates 80% of a board’s routability—has historically required tedious manual arrangement.

Vulcan’s Trials solves placement and routing as a coupled, hardware-accelerated optimization problem:

1. Reads Your Schematic Directly (.kicad_sch + .kicad_pcb): Understands functional circuit blocks, hierarchical sub-sheets, and which decoupling capacitor belongs to which IC pin before moving a single footprint.
2. Harnesses Modern GPU Compute: Offloads 2D/3D Euclidean Distance Field (EDF) obstacle transforms, batch cost evaluations, and Markov Chain Monte Carlo (MCMC) placement scoring to the GPU via Vulkan (wgpu / SPIR-V) and NVIDIA CUDA Driver API (PTX).
3. Zero-Violation Physical & Electrical Rules: Strictly enforces convex polygon courtyard collisions (Separating Axis Theorem), symmetric netclass clearances, RF antenna keepout overhangs, differential pair coupling, and DFM rules.
4. Live KiCad 10 IPC Streaming: Streams placement annealing and trace routing directly into an open KiCad pcbnew canvas at 60 FPS, or runs in its standalone real-time egui 2D viewport and headless CI/CD CLI.

Core Architecture & Capabilities

1. Schematic-Aware Parallel Tempering Auto-Placer

Unlike netlist-only placers that treat every 100nF capacitor on +3.3V and GND as interchangeable, Vulcan’s Trials parses sibling .kicad_sch files to extract functional topology:

• Functional Cluster Extraction: Automatically detects graphical bounding boxes (rectangle / dashed polyline), hierarchical sub-sheets (sheet), and numbered section headers (1. USB & UART BRIDGE, 2. 3.3V LDO POWER, 3. ESP32-C3 MCU, etc.) drawn in the KiCad Schematic Editor.
• Decoupling Capacitor Proximity Binding: Compares schematic symbol coordinates to bind every bypass/decoupling capacitor directly to its parent IC’s power pin (decoupling_targets). During placement, the cost function rewards positioning each capacitor’s pads immediately adjacent to the IC pin it protects.
• Parallel Tempering Simulated Annealing: Runs multiple temperature replicas across all CPU cores (via rayon) and GPU compute units, periodically swapping states between hot (global exploration) and cold (local refinement) replicas to escape local minima, untangle ratsnest crossings, and minimize Euclidean Minimum Spanning Tree (MST) wirelength.
• SAT Courtyard Legalization: Enforces exact convex polygon courtyard clearances using the Separating Axis Theorem (0 courtyard overlaps), while honoring locked mechanical footprints (J1, mounting holes, edge connectors) and off-board RF antenna overhang zones.

2. Automated Pin & Gate Swapping

Before routing even begins, Vulcan’s Trials can untangle ratsnest crossovers at the logical level:

• Bipartite Hungarian Matching: Solves optimal pin assignments across swappable MCU GPIO banks, connector header pins, and multi-unit logic or operational amplifier gates, eliminating unnecessary layer transitions and vias.

3. GPU-Accelerated 3D Negotiated-Congestion Auto-Router

The routing engine combines PathFinder negotiated-congestion rip-up and reroute with GPU-accelerated spatial cost fields:

• Vulkan & CUDA Distance Field Acceleration: Computes multi-layer 3D Euclidean Distance Fields on the GPU using persistent VRAM device buffers (PersistentDeviceBuffers), eliminating PCIe allocation stalls during iterative rip-up passes.
• Symmetric Bidirectional Netclass Clearances: Enforces exact copper-to-copper clearances between every pair of nets A and B: $$ ext{Clearance}(A, B) = rac{ ext{Width}_A}{2} + \max( ext{Clearance}_A, ext{Clearance}_B) + rac{ ext{Width}_B}{2}$$
• Deterministic Fine-Pitch Escape Stubs: Automatically generates staggered pin-escape channels ($\Delta \ge 0.75 ext{ mm}$) for $0.5 ext{ mm}$ pitch QFN, USB-C receptacles, and quadrant dog-bone / microvia BGA fanouts so via annular rings never choke adjacent pin routing corridors.
• Dynamic Push-and-Shove (NudgeEngine): Dynamically nudges unlocked passive components and flexes existing tracks in continuous coordinates to open blocked routing channels when congestion peaks.
• Automated Ground-Plane Via Stitching: Recognizes copper pour zones (F.Cu and B.Cu GND planes) and automatically places ground return and plane-stitching vias for isolated SMD pads and high-speed signal transitions.

4. High-Speed Digital, Topological & Signal Integrity Suite

• Coupled Differential Pair Router: Simultaneous dual-wavefront A* search maintaining constant differential gap (diff_pair_gap), symmetric via transitions, neck-down rules near fine-pitch pads, and automatic intra-pair phase bump matching within $\pm 0.05 ext{ mm}$.
• Serpentine / Trombone Length Tuning: Automated accordion meander generator for matched-delay buses (DDR, SDIO, QSPI, RMII) with configurable amplitude and miter radius.
• Organic / Any-Angle Topological Routing: TopoR-style Delaunay triangulation and rubber-band continuous tangent-arc routing, paired with post-route trace glossing, stair-step removal, and iterative via minimization.
• SI / PI & DFM Hardening: Penalizes parallel coupled trace runs exceeding crosstalk limits ($L_{ ext{coupled}}$), avoids reference plane split crossings, prevents solder-mask slivers and acid traps, and delegates native teardrops.

5. Real-Time Telemetry GUI, KiCad IPC & AI Agent MCP

• Interactive 2D Viewport (eframe / egui): Live pan/zoom PCB canvas with toggleable layers (F.Cu, B.Cu, Courtyards, Ratsnest, Vias, Keepouts, Reference Designators), interactive guided river/bus bundle sketching, and real-time CPU Load % and Vulkan/CUDA GPU Load % sparklines.
• KiCad 10 Live IPC Sync: Connects directly to KiCad’s live IPC socket to stream component placement and trace routing updates at 60 FPS without reloading files.
• Built-in MCP Server: Exposes a Model Context Protocol (MCP) interface so autonomous AI coding and hardware agents can inspect boards, run placement/routing trials, and validate DRC results programmatically.

Commercial EDA Feature Comparison

Quick Start & Installation

1. Install via KiCad Plugin and Content Manager (PCM)

In KiCad (8.0, 9.0, or 10.0), open Plugin and Content Manager → Settings (gear icon) → Add Repository and add:

https://infernoembedded.github.io/vulcans-trials/repository.json

Then search for Vulcan’s Trials in the Plugin Manager and click Install.

2. Build from Source (Rust + Vulkan / CUDA)

git clone https://github.com/InfernoEmbedded/vulcans-trials.git
cd vulcans-trials
cargo build --release

# Run built-in self-test suite (verifies parser, GPU compute, placer, and router)
./target/release/vulcans-trials --self-test

3. Launch the Interactive GUI

./target/release/vulcans-trials   --input /path/to/board.kicad_pcb   --output /path/to/board_routed.kicad_pcb

4. Run in Headless CLI Mode (CI/CD & Batch Trials)

# Full Trial: 120s Parallel Tempering Auto-Place + 10-pass Negotiated-Congestion Auto-Route
./target/release/vulcans-trials   --headless   --mode both   --duration 120   --passes 10   --lock J1,U3,J2   --input examples/esphome_1wire_sensor/esphome_1wire_sensor.kicad_pcb   --output /tmp/esphome_1wire_sensor_routed.kicad_pcb

# Verify zero DRC violations and zero unconnected items with kicad-cli
kicad-cli pcb drc   --output /tmp/drc_report.json   --format json   /tmp/esphome_1wire_sensor_routed.kicad_pcb

Links & Resources

• GitHub Repository: github.com/InfernoEmbedded/vulcans-trials
• End-to-End Tutorial: ESP32-C3 1-Wire Sensor Walkthrough (TUTORIAL.md)
• Roadmap & Architecture: Commercial EDA Feature Matrix (ROADMAP.md)
• KiCad PCM Repository URL: https://infernoembedded.github.io/vulcans-trials/repository.json
• License: GNU General Public License v3.0 only (GPL-3.0-only)